1. Field of the Invention
The present invention is directed to a method for manufacturing complementary MOS field effect transistors in very large scale integration (VLSI) technology wherein gate electrodes are provided with a spacer oxide in order to reduce the underdiffusion of the implanted source/drain regions under the gate area.
2. Description of the Prior Art
In the manufacture of very large scale integrated circuits having structural dimensions on the order of one micron, parasitic effects such as source/drain overlap capacitances, voltage punch-through effects from drain to source, and the so-called "hot electron" effects induced by the high electrical field strengths at the drain increase significantly at a supply voltage of about five volts. The first named effect reduces the switching speed. The punch-through leads to an inadequate inhibiting capability of the transistor. The hot electron effect causes a long term instability of characteristics.
For suppressing these effects, MOS field effect transistors having a suitable pre-arranged profile of the source/drain diffusion have been proposed. By what is referred to as a "source/drain pull-back" described in European Patent Application No. 0 123 182 as well as in a report by K. Ohta et al in IEEE ED-27 (1980), pages 1352-1358, the source/drain diffusion can be pulled back from the gate edge in order to obtain a reduction of the overlap capacitances.
Transistors having a lightly doped connection region to the channel, and referred to as lightly doped drain (LDD) transistors are described in a report by S. Ogura et al in IEEE ED-27 (1980), pages 1359-1367. Transistors referred to as lightly doped drain double diffused transistors are described in a report by S. Ogura et al in IEDM (1982), pages 718-721. Transistors referred to as buried channel lightly doped drain transistors are described in a report by S. Megura et al in IDEM (1983), pages 59-62. The aforementioned transistors lead to improved punch-through behavior and to a noticeable reduction of the hot electron effects.
A method of the type initially described is disclosed, for example, in the aforementioned European Patent Application No. 0 123 182. In this method, there is an attempt made to prevent under-diffusion of the MOS transistor gate due to a pull-back from the gate edge by providing a spacer oxide which is formed by re-oxidation of the polysilicon gate before the source/drain implantation.